1. Field of the Invention
The present invention relates to Electrostatic Discharge (ESD) protection devices. These on-chip semiconductor structures protect circuits from ESD pulses.
2. Description of Related Art
ESD protection devices known in the art are transistors (PMOS/NMOS), thyristors or other devices, which are able to withstand ESD pulses. Most devices of this kind are called ‘snap back’ devices, because of their specific IV characteristic, which comprises a low-resistive mode of operation, which is activated at a given bias voltage, called the trigger voltage. This level of biasing causes equivalent parasitic bipolar transistors to become active in the device. The activation of the parasitic bipolar transistor is only possible when an internal bias has been created, as will be explained in more detail further on.
One of the main goals in the optimization of ESD protection devices consists in finding ways of decreasing the trigger voltage and current, i.e. to have the device snap back at lower ESD stress bias levels. In the state of the art, the way of doing this has been mainly based on trying to increase the substrate current, in order to obtain the necessary internal bias at lower external bias levels or to increase the avalanche current generation in ESD conditions by increasing the device normal operation current (e.g., in the channel, in the case of an NMOS device). Prior art publications dealing with this approach are:                Duvvury et al., “Substrate Pump NMOS for ESD Protection Applications”, Proceedings EOS (Electrical Overstress/ESD symposium), 2000, page 7–17.        Y. Blecher, R. Fried “Zener Substrate Triggering for CMOS ESD Protection Devices”, Electronic Letters, vol. 32, no. 22, 24th Oct. 1996, page 2102–2103.        A. Amerasekere et al, “Substrate Triggering and Salicide Effects on ESD Performance and Protection Circuit Design in Deep Submicron CMOS Process”, Proceedings IEDM 1995, page 547–550.        
The known techniques of enhanced substrate current generation are complex to realize. They require the design of additional control circuitry and take more design area.